ADCs which utilize CDACs, and in particular ADCs which utilize CDACs to convert analog signals to a digital signal are known. ADCs typically are classified according to two parameters: (i) whether the ADC can monitor only a single analog input at any one time (a single input ADC) or whether the ADC can continuously monitor differential inputs (a differential input ADC), and (ii) the internal architecture of the ADC. Two known ADC internal architectures may be referred to as "single ended" and "differential." A single ended ADC architecture means that the ADC has one feedback path to a single CDAC which is coupled to only one of the analog inputs of the ADC's voltage comparator. A differential ADC architecture means that the ADC has two parallel feedback paths (parallel in the sense that they always transmit the same feedback information at the same time) coupled to individual CDACs with one CDAC being connected to the positive input of the ADC's voltage comparator and the other CDAC being connected to the negative input of the ADC's voltage comparator.
Single input ADCs have a single analog input whose signal is measured against a fixed voltage level which is typically ground. ADCs with differential inputs measure the difference between the voltages at the two inputs.
Based upon the above described parameters, the following classifications of ADCs are known: the use of a single-ended architecture to implement a single input ADC, the use of a differential architecture to implement an ADC with a single input, and the use of a differential architecture to implement an ADC with differential inputs.
Known techniques for implementing a single input ADC with a single-ended architecture may result in the occurrence of least two known problems: (1) injection of an error charge into the output signal of the CDAC, and (2) a prohibitively large ratio of the most significant bit (MSB) capacitor to the least significant bit (LSB) capacitor for high resolution ADCs. Several attempts to resolve these deficiencies have been made. For example, the injected error charge may be balanced by providing a "dummy" capacitor array coupled to the normally grounded comparator input. The dummy array results in similar error charges being injected into both inputs of the comparator, in which case, the common mode rejection of the comparator acts to reduce the effects of the error charge.
The deficiency related to the prohibitively large ratio of MSB capacitor to LSB capacitor may be reduced by coupling part of the CDAC's capacitor array to the output of the CDAC through a scaling capacitor. For example, a twelve bit ADC (having twelve capacitors) normally requires that the largest capacitor be 2.sup.11 times greater in size than the smallest capacitor. Coupling a scaling capacitor between the output and, for example, six of the capacitors reduces this requirement to 2.sup.5 greater than the smallest capacitor (because the two groups of six capacitors may be scaled as individual DACs).
However, both of these known solutions may cause other problems. For instance, a dummy capacitor array consumes the same amount of die area, on an integrated circuit, as the capacitor array of the actual CDAC since the dummy array must have the same layout to properly offset the error charge. Also, the capacitance of the scaling capacitor may be significantly affected by the parasitic capacitance of an integrated circuit layout. This may make it difficult to predictably ratio the capacitors coupled to the output of the CDAC through the scaling capacitor with respect to those capacitors which are not coupled to the output of the CDAC through the scaling capacitor. An error in ratioing may result in a differential linearity error for the CDAC at the transition between those capacitors which are and are not coupled to the CDAC's output through the scaling capacitor.
Known implementations of both single input and differential input ADCs with a differential architecture also suffer from at least three known deficiencies: (1) differential ADCs consume twice the die area, for the CDAC portion, compared to a single-ended implementation of a single input ADC (without a dummy array) because two CDACs with identical capacitor arrays are typically required, (2) a prohibitively large ratio of MSB capacitor to LSB capacitor for high resolution ADCs, and (3) additional circuitry is required to cancel the common mode voltage (CMV) to within the common mode range (CMR) of the ADC's voltage comparator. The CMR of a voltage comparator is defined to be the range of input voltages which, when applied to both inputs, will not cause gain degradation.
There are no known solutions for the large die area consumed by ADCs, of either the single input or differential input type, implemented with a differential architecture.
As with known single input ADCs implemented with a single-ended architecture, the prohibitively large ratio of MSB capacitor to LSB capacitor may be reduced by coupling part of the capacitor array of each CDAC to the output of the respective CDAC through scaling capacitors. Unfortunately, as described above, the capacitance of the scaling capacitor may be significantly affected by the parasitic capacitance of an integrated circuit layout making it difficult to predictably ratio the capacitors for each CDAC capacitor array.
In view of the foregoing, it would be desirable to provide an improved analog-to-digital converter circuit using comparator coupled capacitor digital-to-analog converter circuits that require reduced die area.
It would be further desirable to provide an improved high resolution analog-to-digital converter circuit using CDACs which avoids the affects of parasitic capacitance on scaling capacitors.
It would further be desirable to provide an improved analog-to-digital converter circuit using CDACs, of certain ADC categories, that uses simple circuitry to reduce the CMV to be within the CMR of the voltage comparator.
It would further be desirable to apply simple circuitry, for reducing the CMV of an ADC to within the CMR of its voltage comparator, to the dummy CDAC of an ADC with a single input and a single-ended architecture to achieve an ADC with differential inputs.
It would further be desirable to provide an improved analog-to-digital converter circuit using CDACs, of certain ADC categories, that uses simple circuitry to achieve bipolar operation.